Information storage and transfer system



P. MALLERY Aug. 1,1967

INFORMATION STORAGE AND TRANSFER SYSTEM 3 Sheets-Sheet l Filed May 16, 1965 Qqbk Muga..

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/NVE/VTOR F. MALLERV ATTORNEY Augl, 1967 P. MALLERY 3,334,337

INFORMATION STORAGE AND TRANSFER SYSTEM Filed May 16 1963 5 Sheets-Sheet :i:

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Aug. 1, 1967 i. MALLERY 3,334,337

INFORMATION STORAGE AND TRANSFER SYSTEM Filed May 16, 1963 Sheets-Sheet C E r//VE SOURCE ACT/VA TED f, COUN7 SOURCE /a t E/r PULSE SOURCE 25 AND 2 E PHASE ADVANCE PULSE SOURCE 29 s@ E/RSr t@ A PHASE PR/ME PULSE SOURCE 2/ CYCLE C E/RSr FORWARD @VCL E A PHASE ADVANCE PULSE SOURCE 27 t4 AND A PHASE S'EP PULSE SOURCE /4 f5 B PHASE PLP/ME PULSE SOURCE 33 t E/r PULSE SOURCE 25 AND B PHASE 6 ADVANCE PULSE SOURCE 29 s@ L lSECOND t, A PR/ME PULSE SOURCE 3/ CYCLE C SECOND FORWARD @VCL/5 t A PHASE ADVANCE PULSE SOURCE 27 5 AND PHASE STEP PULSE SOURCE /6 t9 B PHASE PR/ME PULSE SOURCE 33 j tm PR/ME PULSE SOURCE 2O E/RSr REVERSE CYCLE 7, A PHASE STEP PULSE SOURCE /4 l2 PR/ME PULSE SOURCE 20 C SECOND REVERSE CYCLE L tu B PHASE STEP PULSE SOUPCE /6 United States Patent O 3,334,337 INFRMATION STURAGE AND TRANSFER SYSTEM Paul Mallery, Murray Hill, NJ., assigner to Bell Telephone Laboratories, Incorporated, New York, N.Y., a corporation of New York Filed May 16, 1963, Ser. No. 280,891 7 Claims. (Cl. 340-174) ABSTRACT F THE DISCLOSURE Independent write and read rates are achieved in shift register operation by associating a stage of an auxiliary counter with each stage of the shift register. When a bit stream is advanced through the shift register, a set state is advanced to the counter stage corresponding to the shift register stage occupied by the foremost bitvof that stream. Interrogation is by means of resetting the counter. Only the set stage resets, and in so resetting interrogates destructively the corresponding shift register stage. Simultaneously, the counter stage corresponding to the shift register stage occupied by the next subsequent bit is set.

This invention relates to information handling systems. More particularly, this invention relates to an information storage and transfer system that may be used as a buffer storage between information handling systems that operate at different processing rates.

In the transfer of information from one information handling system to another, for example, from a computer to a transmission system, difficulties may arise because the rates at which the computer handles information may differ from that of the transmission system. Moreover, the transmission system may be called upon to service other computers which operate at still different processing rates. In addition, the various computors and transmission systems frequently operate with different word lengths. In this connection, a word length is the number of binary coded information bits which constitute meaningful information in the logic orga-nization in which the particular system operates. That is, the word length or block handled by a particular computor may be, for example, ten, twelve or one hundred binary digits or bits while the word block handled by the transmission system may be twenty-six bits. Therefore, it is frequently diiiicult, among other things, t0 synchronize these systems to a common timing reference. In order to transfer information between two such systems, an information storage, commonly termed a buffer storage, is required which can operate at information rates compatible with both systems and which either has a controllably variable word length or, preferably, is operable independent of word length.

Accordingly, an object of this invention is a new and improved buffer storage system.

A further object of this invention is a system for transferring information between information handling systems that operate at different processing rates.

A still further object of this invention is a buffer storage which makes an information transmission system compatible with a variety of information processing systems which operate at a variety of processing rates and/ or word lengths.

These and other objects of this invention are realized, in one illustrative embodiment thereof, comprising a shift register including a plurality of stages capable of having a sequence of binary bits shifted therealong and a reversible counter or stepping switch also having a sequence of stages each of which is associated with a different stage of the shift register. The advance of a sequence of information bits through the stages of the shift register is paralleled by the advance of an identifying condition from stage to stage 3,334,337 Patented Aug. l, 1967 ICC through the counter. For read out, the identifying condition is stepped backwards through the counter from stage to stage thereby producing at each stage a signal for interrogating the associated shift register stage. The output of each shift register stage is sensed by conventional means.

Thus, in accordance with this invention, it is a feature thereof that the read out of each stage of a shift register is accomplished in situ by applying a read-out pulse to a reversible counter which in response thereto provides a signal for interrogating an associated shift register stage each time the counter is stepped backward one stage.

The invention and the objects and features thereof will be understood more fully from a consideration of the following detailed description taken in conjunction with the accompanying drawing in which:

FIG. 1 depicts one specific illustrative buffer storage circuit in accordance with this invention;

FIGS. 2a, 2b, 2c, 3a, 3b, 3c, 4a, 4b, 4c, 4d and 4e illustrate the various transfluxors of the buffer storage circuit of FIG. l in the various flux patterns into which they are driven during the operation thereof; and

FIG. 5 is a schedule of drive pulse deliveries designating the pulse sources for their provision in accordance with this invention.

It is to be understood that the figures are not necessarily to scale, certain dimensions thereof being exaggerated for the purpose of illustration.

In FIG. 1 there is shown a buffer storage circuit 10 comprising a reversible counter or stepping switch C and a shift register SR. The counter C includes a plurality of stages C0, C1, C2, C3 C0. Each counter stage includes a transfluXor 11 bearing a subscript corresponding to that of the stage.

The transfluXors 11 are of a magnetic material characterized by a substantially rectangular hysteresis characteristic and each includes a plurality of apertures therein. Specifically, transuxor includes a relatively large central aperture 12 and two smaller radial apertures 1311 and 1301 which define one input, two middle and one output leg, i1, m11, m2 and o1, respectively, each being equally ux limited. For convenience, each leg is taken as carrying one unit of flux. The remaining counter transfluxors 111 through 11n include, in addition to the sole central aperture, four radial apertu-res, 1311, 1312, 1301 and 1302, respectively, and defining two input, four middle and two output legs, i1, i2, m1, m2, m3, m4 and 01 and 02, having equal flux capacity. The additional apertures add to the transfluxor the capability of having flux switched thereabout for purposes which will become apparent hereinafter. For consistency of designations among the various transfluxors, the apertures to the left (as viewed in FIG. 1) of radial aperture 1311 are designated input apertures and those to the right of radial aperture 1301 are designated output apertures. However, as will become apparent hereinafter, when the counter C is stepped backward, legs 02 and i2 perform functionally as the input and ouput legs, respectively. For simplicity these reference designations are shown only in connection with transuxor 111.

An A phase pulse source 14 designated the A step pulse source is coupled to counter transliuxor 110 and the even numbered counter transuxors 112 11n by means of a conductor 15 threaded serially and in the same sense through the central apertures thereof. Similarly, a B phase step pulse source 16 is coupled to the odd numbered counter transiluxors 111, 113 et seq. by means of a conductor 17 threaded serially in the same sense through the central apertures thereof. Both conductors 15 and 17 terminate at ground potential. A count pulse source 18 is coupled to the counter transfluxoi 110 by means of a conductor 19 threaded through the input radial aperture 1311 thereof. A prime pulse source 20 is coupled serially to counter transiluxors 111, 112,

113 11n by means of a conductor 21 threaded in an alternating sense through the apertures 1311, 1312 and 1302 of each counter transuxor 111, 112, 113 1111. Conductor 21 also is terminated at ground potential.

Transfer loops couple together successive counter transuxors by means of a plurality of conductors 22 each of which is threaded in the opposite sense through the Output radial aperture 1301 and the input radial aperture 1311, respectively, of successive counter translluxors. Each transfer loo-p includes a 'resistance R. In addition to the aforementioned transfer loops, another transfer loop couples together counter transfluxors 110 and 111 by means of a conductor 23 threaded in the same sense through the input apertures 1311 of counter transfluxor 110 and the input aperture 1312 of transfluxor 111. This transfer loop also includes a resistance R. Similarly, additional transfer loops couple together the counter transuxors 111, 112, 113 11n by means of a plurality of conductors 24 threaded in the opposite sense through the output aperture 1302 and the input aperture 1312 of successive transuxors, respectively. Here too, the transfer loops include resistors R. The various transfer loops bear subscripts to denote the transuxors coupled thereby.

The resistances in the various transfer loops may vary in accordance with this invention from a minimum value representing the inherent resistance of the transfer loop to a maximum value related in a well known manner to the amplitude of the prime pulses described hereinafter. However, because these resistances fulfill well known functions, further description thereof is deemed unnecessary and most of their subscripts are omitted for the sake of clarity.

The shift register SR includes a plurality of stages SR1, SR2, SRS SRn. Each shift register stage includes a pair of transuxors in an arrangement commonly termed two-core-per-bit. This arrangement is operated 'in a storage and a transfer phase as will become apparent hereinafter, and the transfluxors are alternately referenced A1, A2, A3 A11, and B1, B2, B3 Bn to correspond respectively to these operational phases.

Each A transfluxor includes one central and two radial apertures as does counter transuxor 1111 defining, as above, four flux carrying legs, two middle legs m1 and m2, an input leg i1 and an output leg 01. Each B transuxor includes not only one central and two radial apertures but an additional radial aperture which defines in each B transuxor an additional middle leg m1, and an additional or second output leg 02 having equal flux capacity. The shift register B transfluxors have no leg m3. The designation of the apertures and legs of the various transfluxors correspond to that designation used in connection with counter transfluxors 110 and 111. For simplicity, the designations for the remaining transfluxors are omitted from the drawing.

A bit pulse source 25 is coupled to the shift register transfluxor A1 by means of a conductor 26 threaded through the input aperture 1311 thereof. An A advance pulse source 27 is coupled to each shift register transuxor A1, A2, A3 An by means of a conductor 28 threading in the same sense serially the central aperture 12 of these transfluxors and terminating at ground potential. Similarly, a B advance pulse source 29 is coupled to each shift register transfluxor B1, B2, B3 B1n by means of a conductor 30 threading in the same sense serially the central aperture 12 of these transfluxors and terminating at ground potential. An A phase prime pulse source 31 is coupled to each shift register A transuxor and each counter transfluxor by means of a conductor 32 threading serially in the same sense the sole input and output apertures 1311 and 1301 of shift register transiluxors A1, A2, A3 An and the sole input and output apertures of counter transuxor 110. Conductor 32 also threads serially in one sense the input aperture 1311, and in the opposite sense the output aperture 1301 and the output aperture 1302 of each counter transuxor 111, 112, 113 1111. The conductor 32 terminates at ground potential. A B phase prime pulse source 33 is coupled to each Shift register B transiluxor by means of a conductor 34 threading serially in one sense the sole input aperture 1311, and in the opposite sense the second output aperture 1302 and the first output aperture 1301 successively of each transiiuxor B1, B2, B3 Bn and terminating at ground potential.

The shift register A and B transiluxors are alternately coupled together by two transfer loop sets. One transfer loop set comprises a plurality of conductors 35 each of which threads in the opposite sense the sole output aperture 1301 of each A transfluxor and the sole input aperture 1311 of the next B transtluxor. The conductors 35 bear subscripts denoting the shift register stage to which they correspond. The other transfer loop set comprises a plurality of conductors 36 each of which threads in the opposite sense the output aperture 1301 of each B transiiuxor and the sole input aperture 1311 of the next succeeding A transuxor. The conductors 36 also bear subscripts denoting the transfluxors coupled thereby. Because stage n is the terminal stage of the shift register it includes only one transfer loop comprising a conductor 35. The shift register B transliuxors are coupled to the associated counter transfluxor by a transfer loop set, each loop comprising conductor 37, threading in the opposite sense the input aperture 1312 of the counter transfluxor and the output aperture 1302 of the associated shift register B transuxor. Each conductor 37 bears subscripts denoting the counter stage to which it corresponds. Each conductor 35, 36 and 37 includes a resistance R. A timing circuit 38 is connected to each pulse source 14, 16, 18, 20, 25, 27, 29, 31 and 33 by means of conductors illustrated in a representative form by line 39.

Sensi-ng the output of the shift register SR is accomplished through sensing circuit 40 which is coupled to each shift register B transiluxor by means of a conductor 41 threading serially the output aperture 1302 of successive shift register B transuxors and terminating at ground potential. Sensing circuit 40 is adapted to receive the outputs of the shift register in successive time slots as will appear hereinafter.

The various transfluxors of the illustrative buffer storage circuit of FIG. l and the flux patterns occurring therein will be designated and discussed separately for providing a convenient reference in the later discussion of the operation of the buffer storage circuit. In this connection, FIG. 2a shows a transuxor A having a large central aperture 12 and two radial apertures 1311 and 1301 defining the legs z'1, m1, m2 and o1 as described hereiribefore. Transfluxor A' represents not only the shift register A transfluxors but also the counter transfluxor 110. The zero or clear state is characterized as magnetic flux directed in the clockwise direction about the central aperture 12, that is, as magnetic flux directed upward in legs i1 and m1, and downward in legs m2 and 01 as viewed in the figure.

FIGS. 2b and 2c illustrate the three-aperture transfluxor A' of FIG. 2a including further flux patterns to which it may be driven during operation. Specifically, in FIG. 2b, the flux pattern corresponds to a stored one state characterized by magnetic flux directed counterclockwise about the radial aperture 1311 and clockwise about the radial aperture 1301, that is downward in legs i1 and 01, and upward in legs m1 and m2 as viewed in the figure. FIG. 2c illustrates the stored one state after the transfluxor A' is primed. The magnetic flux is dilrected clockwise about radial aperture 1311 and counterclockwise about radial aperture 1301 or upward in legs i1 and 01, and downward in legs m1 and m2 as viewed FIGS. 3a, 3b and 3c illustrate a four-aperture transfluxor B in the various flux states to which it is driven during operation of the 'buffer storage circuit of FIG. 1.

The transtluxor B of FIG. 3a includes a central aperture 12, ya single input radial aperture 13 11 `and two output apertures 1301 and 1302 dening legs i1, m1, m2, o1, m4 and 02.

The zero or clear state is shown as magnetic flux in the clockwise direction about aperture 12, that is, liux directed upward in legs i1 and m1 and downward in legs m2, m4, 01 and 02 as viewed in the figure. The stored one state for transiiuxor B is illustrated in FIG. 3b as flux directed counterclockwise about the radial aperture 1311 and clockwise about radial apertures 1301 and 1302, that is, upward in legs m1, m2 and m4, and downward in legs i1, o1 and o2 as viewed in the figure. The one prime state for transfluxor B is shown in FIG. 3cl as flux directed clockwise about radial aperture 1311 and counterclockwise about radial apertures 1301 and 1302 or as flux directed downward in legs m1, m2 and 111.1, and upward in legs i1, o1 and o2 as viewed in the figure.

FIGS. 4a, 4b, 4c, 4d and 4e illustrate a tive-aperture transfl'uxor 11 in the various flux states to which it is driven during operation of the buffer storage circuit of FIG. 1. The transfluxor 11 of FIG. 4 includes a large central aperture 12, two input apertures 1311 and 1312 and two output apertures 1301 and 1302 defining legs i1, m1, i2, m3, m2, o1, m1 and 02, respectively.

The Zero or clear state is shown in FIG. 4a as flux directed in the clockwise direction about aperture 12, that is, as flux directed upward in legs i1, i2, m1 and m3, and downward in legs m2, m4, 01 and o2 as viewed in the ligure. FIG. 4b shows the one or set state as ux directed counterclockwise about radial aperture 1311 and clockwise about radial aperture 1312 1301 and 1302, that is as flux directed downward in legs i1, m3, o1 and 0-2, and upward in legs m1, i2, m2 and m4 as viewed in FIG. 4b. The one prime state is shown in FIG. 4c as uX directed clockwise about radial apertures 1311, 1312 and 1302 and counterclockwise about radial aperture 1301, that is as flux directed downward in legs m1, m3, m2 and 02, and upward in legs 1'1, i2, o1 and m1 as viewed in FIG. 4c.

The transiluXor 11 is capable of assuming another ux pattern corresponding to a stored one or set state as shown in FIG. 4e. In this ligure, the flux about radial aperture 1302 is in the counterclockwise direction and the remaining uX is in the clockwise direction about apertures 1312, 1301 and 1311, that is, the flux is directed downward in legs m4, 01, m3 and m1, and upward in legs 02, m2, i2 and i1 as viewed in FIG. 4e. Similarly, the one prime condition can be represented by a second tiux pattern as shown in FIG. 4d. There the ux is drected in a clockwise direction about radial apertures 1302, 1301 and 1311 and in a counterclockwise direction about aperture 1312, that is, the ux is directed downward in Ilegs 011, 02, i2 and m1 and upward in legs m4, m2, m3 and i1 as viewed in FIG. 4d. The flux patterns of FIGS. 4d and 4e are observed when the counter is stepped back- Award for read out as will become apparent from the followin-g description of the operation of the butter storage circuit of FIG. 1.

The operation of the buffer storage circuit of FIG. 1 is considered for the following illustrative assumed sequence of operation wherein a binary zero is introduced as the first bit, a binary one is introduced as the second bit, the rst bit is read out, and the second bit is read out. In this connection, the two information bits described may be assumed to constitute only a portion of a word in the logic system of the source. It is to be understood that the time designations in the following description of the operation are intended merely to serve as chronological benchmarks for the entire operation described for the illustrative embodiment. These times are not to be confused with a normal cycle of operation in the conventional usa-ge of the term. The correspondence between the chronological benchmarks and a cycle of d register and counter is shown in the legend to the left of FIG. 5 and'will be discussed hereinafter.

Initially, all the transfluxors of both the shift register and the counter are in a clear state. That is, all the magnetic iiuX through the legs in each transtiuxor is directed in a clockwise direction about the central aperture as shown in FIGS. 2a, 3a and 4a.

Operation in accordance with this invention is initiated at time t1 by activating under the control of timing circuit 38 which similarly controls the other pulse sources herein described, the count pulse source 18 as designated in FIG. 5, thereby pulsing conductor 19 for driving counter transliuxor 110 to the stored one state shown in FIG. 2b. For this purpose, pulse source 18 as well as each'of the pulse sources described in connection with this invention is entirely conventional and may comprise any well known electron tube device, magnetic core drive or transistor driven pulse transformer which applies a conventional drive pulse. Similarly, timing circuit 38 may be any well known timing circuit capable of synchronizing the energization of the pulse sources to which it is connected.

At time t2, the bit pulse source 25 is activated initiating a normal shift register cycle of operation. Since it is intended to store a zero at this time, no pulse is applied thereby to conductor 26 for driving the ux in shift register transfluxor A1. Transfluxor A1, thus, remains in a clear state which signifies a stored zero. In 'this connection, a pulse or the absence of a pulse from source 25 determines whether or not linx in transfluxor A1 switches and, consequently, whether or not a one or a zero is stored therein. Simultaneously, with the activation of bit pulse source 2S at time t2, the B phase advance pulse source 29 is activated thereby pulsing conductor 30 tending to drive the shift register B transfluxors tothe clear state shown in FIG. 3a. The B transiiuxors already are in the clear state, however, and, consequently, there is no switching of iiuX therein in response to this pulse.

At time t3 an A phase prime pulse source 31 is activated thereby pulsing conductor 32 for driving the flux in counter transtiuXor 1111 into the one primed pattern shown in FIG. 2c and, accordingly, initiating a normal forward counter cycle. In this connection, the prime pulse is limited in amplitude to a value less than that required for ux switching around a central aperture 12 and of sufficient duration to switch ux about a radial aperture. These limitations are well known in transfluxor diodeless shift registers in order to avoid the false propagation of information. Although conductor 32 also couples legs i1 and o1 of each of the shift register A transuxors and each'counter transfluXor 111, 112, 113 110, no priming thereof results because for the stored zero condition which obtains in the transiiuxors at this juncture in the operation the legs coupled by conductor 32 either are saturated in the direction in which they are urged by the prime pulse or have available to flux switched therein no ux closure path about the radial apertures.

At time t4, shift register A advance pulse source 27 and counter A phase step pulse source 14 are activated thereby pulsing conductors 28 and 15 respectively for driving shift register transfluxor A1 and counter transuxor 110 to the clear state shown in FIG. 2a. Transuxor A1 already is in the clear state and, accordingly, exhibits no significant response to the pulse from source 28. However, transtluxor 110 including a one prime is driven into the clear state. The flux lswitching in leg 01 of transfluxor 110 induces a pulse in conductor 2201 which drives counter transiiuxor 111 to the stored one state shown in FIG. 4b thus completing a normal forward counter cycle. At this juncture inthe operation a stored zero appears in shift register transtiuxor B1 and a stored one appears in the associated counter transfluxor 111.

At time t5, the B phase prime pulse source 33 is activated thereby pulsing conductor 34, tending to switch the liux in the B transtiuxors into the clear pattern shown in FIG. 3a and, accordingly, completing the rst normal cycle of operation for the shift register. However, n changes in magnetic flux in the shift register B transfluxor occur at time t because transfluxor B1 includes a zero and the remaining B transuxors already are in the clear state. When the transfluxor B1 is in the zero state, the leg i1 thereof coupled by conductor 34 already is saturated in the direction urged by the prime pulse. Legs o2 and o1 of transuxor B1 also coupled by conductor 34 although not saturated in the direction urged by the prime pulse do not have available a flux closure path for any flux switched therein and, accordingly, do not switch.

At time t6, the second bit or a one is stored by activating bit pulse source causing a pulse in conductor 26 for driving the flux in shift register transfluxor A1 into the stored one pattern shown in FIG. 2b. Thus a second normal cycle for the shift register is initiated. Simultaneously, with the activation of the bit pulse source 25, the B phase advance pulse source 29 is activated thereby pulsing conductor 3@ for driving the shift register B transfluxors into the clear condition shown in FIG. 3a. The B transfluxors again still are in the clear condition and, consequently, there is no response to this pulse.

At time t7, the A prime pulse source 31 is again activated causing thereby a pulse in conductor 32 which drives the flux in transfluxor A1 into one prime pattern shown in FIG. 2c. Thus a second normal forward cycle of operation for the counter is initiated.` By this same pulse, the flux in counter transfiuxor 111 is driven into the one prime pattern shown in FIG. 4c. Although the remaining transfluxors A2, A3 An and the counter transfluxors 1111, 112, 113 1111 also are coupled by conductor 32, no switching occurs there because the affected legs already are saturated in the direction urged by the pulse or do not have flux closure paths available.

At time t8, shift register A phase advance pulse source 27 is activated thereby pulsing conductor 28, switching the ilux in transtluxor A1 into the pattern shown in FIG. 2a thereby returning the transfluxor to the clear state. As a result of the switch in flux in leg 01 of transfluxor A1, a pulse is induced in conductor 351 driving the -flux in shift register transfluxor B1 into the one pattern shown in FIG. 3b. Simultaneously, counter B phase step pulse source 16 is activated thereby pulsing conductor 17 for driving the flux in counter transfluxor 111 to the Zero or clear state shown in FIG. 4a. Thus the second normal forward cycle of operation for the counter is terminated. This switching of the flux in transuxor 111, in turn, induces a pulse in conductor 2212 which causes flux in counter transfluxor .112 to switch into the one or set pattern shown in FIG. 4b.

At time t9, the B phase prime pulse source 33 is activated thereby pulsing conductor 34, tending to switch the flux in all the B transfluxors into the one prime pattern shown in FIG. 3c and, accordingly, terminating the second normal cycle of operation for the shift register. As a result of this pulse, the ux in shift register transfluxor B1 is switched into the pattern shown in FIG. 3c. There is no switching in the remaining B transfluxors for the reasons discussed in connection with the operations occurring at time t5. The flux switch in leg 01 of transfluxor B1 induces a pulse in conductor 3612 tending to drive leg i1 of transuxor A2 upward as viewed in FIG. 2a. However, the leg i1 of transfluxor A2 already is saturated upward and no response to the pulse occurs there. At this juncture in the operation a zero is stored in transuxor B2, a one is stored in transfluxor B1, and a one is stored in transuxor 112.

Successive bits are introduced into the shift register in the above manner depending solely on the processing rate and block length characteristics of the source, such as a computer, which may be serviced, the exemplary bits described in the foregoing being propagated through the shift register in the aforementioned manner simultaneously with the introduction of successive bits.

The read out of the bits stored in the shift register depends solely on the processing rate and block length characteristics of the receiving circuits such as a transmission system, for example. Accordingly, regardless of the stage in the shift register to which the first bit has advanced in response to the writing of consecutive bits therein, read out occurs only when the transmission systern signals the counter that it can accommodate information. The transmission system TS of FIG. l so signals the counter by means of a conductor 39a connected to the timing circuit 38 for initiating the read-out sequence as described hereinafter. For simplicity, it is assumed that only the two bits described in detail above are in the shift register and that the first bit to be read out is in shift register transuxor B2. It is to be emphasized that the read-out sequence to be described is for reading out two information bits and if additional bits are to be read out, as may be the case for example if the transmission system accepts blocks of ten bits, repetition of the described read-out cycle for the read out of one bit is correspondingly required.

If a sufiicient number of information bits are written into the shift register to occupy the entire register either because there has been n0 read out or because the read out is not at a fast enough rate to keep up with the writein rate, a store full detector (Sfd) is activated by means of a pulse induced in the store full conductor (Sfc) by ux switching in counter transfluxor 11n through the central aperture 12 of which the conductor is threaded. In this connection the store full detector is any well known detector capable of providing an output signal in response to a ux switching in a magnetic element to which it is connected. The store full detector is connected to the transmission system TS of FIG. l by means of a conductor 39h for transmitting thereto the output signal of the detector. In response to this signal the transmission system signals timing circuit 38 by means of conductor 39a for stopping further input to the register.

In addition, the read-out operation is not initiated until the shift register SR includes a sufiicient number of bits to constitute a word block acceptable to the shift register. For illustration, this word block is taken as two bits. Accordingly, a start read detector (Srd) is connected to counter transfluxor 112 by means of a start read conductor (Src), initiating the read-out cycle response to flux switching in transfluxor 112. The mechanism for initiating the read-out cycle, that is, the reverse cycle of operation for the counter, is by means of a signal transmitted by means of conductor 39C from the start read detector to the transmission system which in response thereto signals timing circuit 3S for initiating the read-out sequence. Accordingly, in response to the signal from the transmission system indicating that space is available therein, timing circuit 38 initiates the following read-out sequence of two read-out cycles by activating pulse sources 20, 14 and 16 as follows.

At time r11, the prime pulse source 20 is activated thereby pulsing conductor 21, tending to drive the ux in all counter transfluxors 111, 112, 113 11n into the one prime pattern shown in FIG. 4d, thus initiating the rst reverse cycle of operation for the counter. At time i111, however, only counter transfluxor 112 is in condition to be switched. The remaining counter transfluxors 11 already are saturated in a direction urged by the prime pulse or do not provide suitable flux closure paths as discussed in connection with the operation at time t5.

At time r11, the counter A phase step pulse source 14 is activated thereby inducing a pulse in conductor 15 for driving counter transuxor 112 to the clear state shown in FIG. 4a thus terminating the rst reverse cycle of 0peration for the counter. The flux switched in leg i2 of translluxor 112 induces a pulse in conductor 2412 driving transfluxor 111 into the stored one or set state shown in FIG. 4e. Thus, there is recorded in counter transfluxor 111 a one while counter transfluxor 112 is driven to a clear state. The switch in ux in the leg i2 of transfluxor 112 also induces an interrogating pulse in conductor 372 tending to switch leg o2 of shift register transfluxor B2 downward as viewed in FIG. 3a. Since a zero is stored in transuxor B2 at this time, leg 02 already is saturated downward and no response to the interrogating pulse results. Consequently, during the corresponding sensing circuit time slot a null indication or a zero output appears and the first read-out cycle terminates. It is noted that read out of shift register transfluxor B2 is nondestructive and a zero remains therein to be propagated through the register in a conventional manner.

At time t12, prime pulse source 20 is again activated thereby pulsing conductor 21 a second time, tending to drive the iiux in all counter transfluxor 111, 112, 113 11n into the pattern shown in FIG. 4d thus initiating the second reverse cycle of operation for the counter. However, at this juncture, only transuxor 111 is in a condition to switch for the reasons discussed in connection with the operation at time t5. Although the flux switched in leg i2 of transuxor 111 induces a pulse in conductor 23, no switching of the iiux in leg i1 of transfluxors 110 results because of the reasons already discussed in connection with the operation at time t5.

At time t13, the B phase step pulse source 16 is activated thereby ind-ucing a pulse in conductor 17 for driving counter transuxor 111 to the clear state shown in FIG. 4a. As was the case at time r11, the next preceding counter transfluxor (here transuxor 110) is driven to the stored one or set state. The switch in ux in leg i2 of transfluxor 111 induces an interrogating pulse in conductor 371 tending to switch leg 02 of shift register transfluxor B1 downward as viewed in FIG. 3a. Since a one prime as shown in FIG. 3c is stored in transfluxor B1 at this time, switching thereof occurs in response to the interrogating pulse. Consequently, during the corresponding sensing circuit time slot a pulse appears indicating a stored one in transfl-uxor B1; thus the second reverse cycle of operation for the counter terminates.

The foregoing read-out sequence is described for reading out of the register between the writing of two successive bits a number of bits which constitute a word inthe logic arrangement of the transmission system. If the relative write and read rates and/ or block length of the transmission system are such that -additional bits are introduced before an entire block of bits is read out of the register thus interrupting the read-out sequence, the write land read pulses may be timed to interleave with each other enabling ostensibly uninterrupted write and read operations. From the foregoing, other timing variations should be evident.

The foregoing operation was initiated under the conditions that the counter included no identifying flux condition therein. If the lbuffer storage circuit has been in use prior to the introduction of the first bit described herein, the identifying condition or set state will be in one stage of the counter as is evident from the foregoing. However, the counter may be cleared merely by pulsing the A phase and'B phase read pulse sources simultaneously under the control of timing circuit 38. On the other hand, operation as described hereinbefore may continue unchanged without clearing the counter rst.

There are various modifications of the organization of the system in accordance with this invention as illustrated in FIG. l. Specifically, the first counter transfluxor 110, as illustrated in FIG. l, includes the set state or identifying condition when all the information bits in the register are read out. Transfiuxor 110 is not necessary, however, if means are provided to drive transfluxor 111 to the set state or condition after the shift register is read out completely and prior .to the introduction of additional bits.

No effort has been made to describe all possible embodiments of the invention. It should be understood that the embodiment described is merely illustrative of the various forms of the invention and Various modifications may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. Ina shift register having a plurality of stages capable of having a sequence of information bits including a foremost bit shifted therealong, read-out means comprising a bistable circuit having set and reset states connected `to each stage of said shift register,

means for setting a preselected one of said bistable circuits -to said set state to correspond to the shift of said foremost bit to the corresponding connected stage of said shift register,

lmeans for resetting said preselected one of said bistable circuits to said reset state,

first means responsive to said resetting for destr-uctively interrogating the connected shift register stage causing the next subsequent bit to become said foremost bit,

second means responsive to said lresetting for set-ting the bistable circuit connected to the next preceding shift register stage in which said next subsequent bit is stored, and

means responsive to the interrogation for sensing the response of the first-mentioned connected shift register stage thereto.

2. In a shift register having a plurality of stages capable of having a sequence of information bits shifted therealong,

a counter having a plurality of bistable stages having set and reset states each of which stage is connected to a different shift register stage,

means for introducing a sequence of information bits into the first stage of said shift register,

means for setting to said set state the coun-ter stage connected to the first stage of the shift register,

means for advancing said sequence of information bits through the stages of said shift register,

means for advancing said set state through the stages of said counter in correspondence with the advance of the first bit of said sequence .of information bits thro-ugh said shift register; and

read-out means comprising means for resetting to said reset state the set counter stage,

means responsive to said resetting of said set counter stage to said reset state for interrogating the corresponding :connected shift register stage,

means responsive to said resetting of said set counter stage to said reset state for setting to said set state the next preceding counter stage, and

means responsive to the interrogation for sensing the response of the connected shift register stage thereto.

3. An electrical circuit comprising a shift register having a plurality of stages capable of having a series of information bits shifted therealong,

a counter circuit having a plurality of stages each connected to a different one of said plurality of stages of said shift register and also having a stage preceding the first of said plurality of stages,

means for .advancing said counter circuit in correspondence with the shift of the first of said series of information bits in said shift register,

means for sequentially reversing said counter circuit when said first of said series of information bits reaches a predetermined stage of said shift register, `and means connected to each stage of said shift register energized responsive -to the sequential reversing of said counter circuit for reading out said series of information bits.

4. A circuit including a shift register comprising a plurality of stages,

each of said stages including a first bistable element,

said shift register being capable of accommodating a sequence of binary coded information bits advanced therethrough,

a counter comprising a plurality of stages each including a second bistable element,

said rst and second bistable elements having set and reset states,

each of said counter stages being directly connected to a different one of the shift register stages,

means for advancing said information bits through said shift register,

means for registering in successive ones of said counter stages said set state indicative of the position in successive shift register stages of the first of said sequence of information bits; and

means for reading information bits out of said shift register comprising means for resetting the second element including said set state from said set to said reset state,

means responsive to said resetting of said second element for driving the corresponding connected rst element to said reset state,

means for sensing the resetting and absence of resetting of said connected rst element, and

means responsive to the resetting of said second ele- Iment for setting to said set state the next preceding second element.

5. An information buffer circuit comprising a shift register circuit having a plurality of stages and being capable of having a plurality of information bits shifted therealong,

a reversible counter having a plurality of stages and being capable of having a single information bit advanced therealong,

coupling means for coupling each of said shift register stages to a corresponding one of said counter stages,

means for advancing said counter simultaneously with the advance of said plurality of information bits in said shift register,

means for reversing said reversible counter responsive to the advance of said single information bit to a predetermined stage for generating interrogating signais in said coupling means, and

read-out means for said shift register energized responsive to said interrogating signals for sensing said plurality of information bits as said counter counts backward from said predetermined stage.

6. A magnetic circuit including a shift register comprising pairs of first and second transfluxors capable of accommodating a sequence of information bits advanced therethrough, a plurality of third transuxors each connected to a different one of said second multi-aperture transfluxors,

said second and third transfiuxors having set and reset states,

means for advancing said information bits through said shift register,

means for registering in successive ones of said third transfluxors said set state indicative of the position in successive ones of said second transuxors of the first of said sequence of information bits,

read-out means including a rst conductor coupling said third transiiuxor,

means for pulsing said first conductor for resetting to said reset state the registering third transfluxor, and

means responsive to said resetting of said registering third transuxor for driving the corresponding connected second transfluXor to said reset state.

7. A magnetic circuit including a shift register comprising pairs of rst and second transfluxors capable of accommodating a sequence of information bits advanced therethrough,

a plurality of third transiiuxors each connected to a different one of said second transuxors,

said second and third transfluxors having set and reset states,

means for advancing said information bits through said shift register,

means for registering in successive ones of said third transuxors said set state indicative of the Iposition in successive ones of said second transuxors of the rst of said sequence of information bits; and

read-out means including a iirst conductor coupled to said third transfluxors,

means for pulsing said first conductor for resetting to said reset state the registering third transfluxor,

means responsive to the resetting of said registering third transuxor for setting to said set state the next preceding third transfluxor,

means responsive to the resetting of said registering third transiiuXor for driving to said reset state the connected second transfluXor, and

means for indicating the resetting and absence of resetting to said reset state of said connected second transfluXor.

References Cited UNITED STATES PATENTS 3,157,863 11/1964 James 340-174 BERNARD KONICK, Primary Examiner.

S. M. URYNOWICZ, Assistant Examiner. 

1. IN A SHIFT REGISTER HAVING A PLURALITY OF STAGES CAPABLE OF HAVING A SEQUENCE OF INFORMATION BITS INCLUDING A FOREMOST BIT SHIFTED THEREALONG, READ-OUT MEANS COMPRISING A BISTABLE CIRCUIT HAVING SET AND RESET STATES CONNECTED TO EACH STAGE OF SAID SHIFT REGISTER, MEANS FOR SETTING A PRESELECTED ONE OF SAID BISTABLE CIRCUITS TO SAID SET STATE TO CORRESPOND TO THE SHIFT OF SAID FOREMOST BIT TO THE CORRESPONDING CONNECTED STAGE OF SAID SHIFT REGISTER, MEANS FOR RESETTING SAID PRESELECTED ONE OF SAID BISTABLE CIRCUITS TO SAID RESET STATE, 